The majority of designs in the consumer electronic industry include an interface between an integrated circuit (IC) and a memory, the memory often known as a synchronous dynamic random access memory (SDRAM). An SDRAM is a memory chip, with different SDRAMs designed to hold different amounts of data and operate at different speeds.
De facto industry standards exist for the interface between an IC and a SDRAM. To better understand the limitations and operation of conventional systems, an example of an IC interfaced to a SDRAM according to the de facto standard is provided, along with write and read operations.
FIG. 1 is a block diagram illustrating a conventional IC 100 connected to standard SDRAM 102. IC 100 has memory controller 104 that operates SDRAM 102 according to the de facto standard for a memory interface. IC 100 reads data from SDRAM 102 during a read operation and writes data to SDRAM 102 during a write operation. Activate and pre-charge are examples of other operations performed by SDRAM 102 at various times. Address and bank select lines 106 are connected between IC 100 and SDRAM 102 and convey memory address location (row and column addresses) signals and bank select (determines source or destination bank) signals from IC 100 to SDRAM 102. Data lines 108 are connected between IC 100 and SDRAM 102 and convey data between IC 100 and SDRAM 102. Data is transmitted in both directions on data lines 108. Each of the above-mentioned lines connects to IC 100 through pins on the exterior of IC 100, most of the pins being controlled by memory controller 104.
Clock line 110 conveys a clock signal from IC 100 to SDRAM 102 and mask lines 112 are used by IC 100 to instruct SDRAM 102 to ignore data appearing on data lines 108. Control lines 114 convey control commands from IC 100 to SDRAM 102, for example read, write, activate, and pre-charge. In the example shown, there is one line for a clock signal, 3 lines for control signals, 2 lines for byte mask signals, 12 lines for memory address signals, 2 lines for bank select signals, and 16 lines for data signals, for a total of 36 pins from IC 100 needed in order to interface to SDRAM 102 according to the de facto standard.
FIG. 2 is a timing diagram illustrating a conventional write operation from the integrated circuit to the SDRAM of FIG. 1. FIG. 2 will be discussed in conjunction with the corresponding structure in FIG. 1. Clock signal 200 is transmitted along clock line 110 from IC 100 to SDRAM 102. Write command 202 is transmitted along command lines 114 to SDRAM 102. At time 201, address 204 is transmitted along address lines 106 and data 206 is transmitted along data lines 108. The timing and operation of the transmission follows the de facto standard for memory interfaces with SDRAM. SDRAM 102 receives data 206 and performs a write operation by putting data 206 in address 204 within SDRAM 102. Mask lines 112 are de-asserted, as indicated by mask signal 208, enabling the storage of the data to the memory. Throughout the specification, DN and AN will refer to particular (N) data that is going to a particular (N) address.
At time 210, IC 100 transmits activate command 212 along command lines 114 to SDRAM 102, along with address 214. SDRAM 102 responds by activating a bank address designated by address 214. Also at time 210, data 216 is transmitted to SDRAM 102. An internal counter (not shown) increments a group of cells (not shown) to which SDRAM 102 writes data each clock cycle. Since one clock cycle has passed, the position is incremented by one. Data 216, which is the next block of data transmitted by IC 100, is written into the next memory cell as indicated by the internal counter of SDRAM 102.
At time 218, no control command is transmitted along command lines 114, and data 220 is transmitted along data lines 108. The internal counter in SDRAM 102 has incremented the group of memory cells to which data 220 is written.
At time 219, no control command is transmitted along command lines 114, and data 222 is transmitted along data lines 108. The internal counter in SDRAM 102 has incremented the group of memory cells to which data 222 is written.
Finally, at time 224, no control command is transmitted along command lines 114, and data 226 is transmitted along data lines 108. Data 226 is the last portion of data written to SDRAM 102 in the write operation, which took 5 clock cycles to complete. During those 5 clock cycles activate command 210 was also transmitted from IC 100 to SDRAM 102.
In FIG. 3, a timing diagram illustrates a conventional read operation from the integrated circuit to the SDRAM of FIG. 1. FIG. 3 will be discussed in conjunction with the corresponding structure in FIG. 1. Clock signal 300 is transmitted along clock line 110 from IC 100 to SDRAM 102. Read command 302 is transmitted along one of command lines 114 to SDRAM 102. At time 301, address 304 is transmitted along address lines 106. The timing and operation of the transmission follows the de facto standard for memory interfaces with SDRAM. SDRAM 102 receives read command 302 and address 304 and prepares the memory cell at address 304 to read out data to IC 100. Mask lines 112 are de-asserted, as indicated by mask signal 308.
At time 310, no control command is transmitted along command lines 114 while SDRAM 102 prepares to read out data to IC 100.
At time 312, IC 100 transmits activate command 314 along command lines 114 and sends address 316 for the bank/row to activate (one skilled in the art will recognize that a bank address is not synonymous with a memory address, but for the purposes of this background the distinction is not important). Also at time 312, SDRAM 102 begins transmitting data to IC 100 as requested by read command 302, 2 clock cycles earlier. Note that the number of clock cycles from the assertion of a read command until SDRAM 102 responds with data is programmable according to the de facto SDRAM standard. The value is programmed by a controller according to it's abilities, the operating frequency and the speed grade of SDRAM 102. For example, values can be set to 1, 2 or 3 clock cycles.
At time 320, IC 100 transmits pre-charge command 322 along command lines 114 and sends address 324 for the bank to pre-charge. Also at time 320, the next data block is transmitted from SDRAM 102 to IC 100. The internal counter (not shown) discussed earlier operates in the same manner for read operations as it does for write operations. Next, mask signal 308 is asserted on mask lines 112. Mask lines 112 control the output enable signals and are timed to precede the data out from SDRAM 102 by two clock cycles, in this example.
At time 328, no control command is transmitted along command lines 114 while data 330, which is the last of the data, is read from SDRAM 102. Over the 5 clock cycles, 3 blocks of data were read out, and activate and pre-charge commands were issued.
The de facto standard was created to operate at a particular point in the trade off of pin count versus memory bandwidth, i.e. the more pins used, the more data may be transferred during a given clock cycle, while fewer pins means lower data transmission. The SDRAM interface often represents the most pin intensive interface in the design. High pin count, in the above case SDRAM 102 uses 36 pins, can result in forcing designs into larger and more expensive packages, either due to the number of pins required or due to the increase in power consumption required to switch all of the output signals.
Accordingly, what is needed is a method and system for reducing pin count in an integrated circuit when interfacing to a memory. The present invention addresses such a need.